The present invention is directed, in general, to integrated circuit amplifiers and, more specifically, to voltage gain cells employing a folded cascade topology.
Voltage gain cells are typically implemented in two stages, as shown in FIG. 2. The transfer function of the circuit is given by:                                           V            o                                V            i                          =                              gm            1                                gm            2                                              (        1        )            
where Vi is the voltage input to differential amplifier GM1, Vo is the voltage output of differential amplifier GM2, gm1 is the transconductance of differential amplifier GM1, and gm2 is the trasnconductance of differential amplifier GM2.
Some voltage gain cells employ external resistors R1 and R2 as shown in FIG. 3 to set the transconductance value gm of each differential amplifier, where the voltage gain becomes:
xe2x80x83gm=1/R.xe2x80x83xe2x80x83(2)
The voltage gain (i.e., transfer function) for the voltage gain circuit in FIG. 3 is therefore:                                           V            o                                V            i                          =                                            R              2                                      R              1                                ·                                    (        3        )            
When implemented with a folded-cascade topology, a two stage voltage gain cell of the type shown in FIG. 3 may be implemented by the transistor-level circuit of FIG. 4, where only the essential components are shown and the common mode feedback is not included.
The implementation of a folded cascade voltage gain cell which is shown includes a first stage having n-channel transistors MNU1 and MND1 receiving the input voltage Vi through positive and negative inputs IN+and INxe2x88x92at the gates of transistors MNU1 and MND1. Resistors R1 are connected between the sources of transistors MNU1 and MND1, and current sources IU1 and ID1 are each connected between the source of one of transistors MNU1 and MND1 and a ground voltage gnd.
Current source IPUL is connected between the drain of transistor MNU1 (node NU1) and a power supply voltage Vdd. The drain of transistor MND1 is connected to the source of p-channel transistor MPU1 (node ND1), which receives a reference voltage Vref at a common gate connection with p-channel transistor MPD1. The source of transistor MPD1 is connected to node NU1 and, through current source IPU1, to the power supply voltage Vdd. The drains of transistors MPD1 and MPU1 are each connected, through a current source IOD1 and IOU1, respectively, to the ground voltage gnd. The positive and negative output signals OUT+and OUTxe2x88x92which form the output voltage Vo are drawn from the drains of transistors MPD1 and MPU1, and couple the first and second stages of the voltage gain cell.
Within the second stage, output signals OUT+and OUTxe2x88x92are connected to the drains of p-channel transistors MPU2 and MPD2, respectively, and to the gates of n-channel transistors MND2 and MNU2, respectively. The drain of transistor MNU2 (node NU2) is connected to the source of transistor MPD2 and to through current source IPU2 to the power supply voltage Vdd. The drain of transistor MND2 (node ND2) is connected to the source of transistor MPU2 and to through current source IPD2 to the power supply voltage Vdd. Resistors R2 are connected between the sources of transistors MNU2 and MND2, and the sources of transistors MNU2 and MND2 and the drains of transistors MPD2 and MPU2 are each connected through one of current sources IU2, ID2, IOD2 and IOU2 to the ground voltage gnd.
Multistage folded cascade voltage gain cells of the type shown in FIG. 4 consume significant power and, because of the number of internal nodes, contain a corresponding number of poles, which limits operational bandwidth. There is, therefore, a need in the art for a folded cascade voltage gain cell having fewer stages and transistors.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in an integrated circuit, a folded cascade voltage gain cell implemented in a single stage by collapsing p-channel transistor branches receiving output currents from two sets of n-channel transistor branches and producing the output voltage into a single set of branches, summing the output currents from two sets of n-channel transistor branches in a single pair of nodes. While power consumption is only slightly improved over multistage folded cascade voltage gain cells, the circuit is implemented with fewer transistors and is therefore smaller and more reliable. Moreover, because only one gain stage is employed with a smaller number of internal nodes, the circuit""s operation contains a smaller number of poles, and bandwidth is improved.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words or phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9corxe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior as well as future uses of such defined words and phrases.